CIRCUITS, APPARATUSES, AND METHODS FOR DELAY MODELS

摘要

Circuits, apparatuses, and methods are disclosed for delay models. In one such example circuit, a first delay model circuit is configured to provide a first output signal by modeling a delay of a signal through a path. A second delay model circuit is configured to provide a second output signal by modeling the delay of the signal through the path. A compare circuit is coupled to the first and second delay model circuits. The compare circuit is configured to compare a third signal from the first delay model circuit and a fourth signal from the second delay model circuit, and, in response provide an adjustment signal to adjust the delay of the second delay model circuit.

主权项

1. An apparatus, comprising:
a buffer circuit configured to receive an external clock signal and provide a buffered clock signal in response; a clock generation circuit configured to receive the buffered clock signal and a control signal, and configured to provide an output signal in response; a feedback delay model circuit configured to model a delay and provide a delayed clock signal in response; and a first compare circuit configured to compare the delayed clock signal and the buffered clock signal and provide the control signal in response; wherein the feedback delay model circuit comprises:
an accurate delay model circuit;a low power delay model circuit configured to be adjustable responsive to an adjustment signal;a second compare circuit coupled to the accurate and low power delay model circuits and configured to provide the adjustment signal responsive to a comparison of the accurate and low power delay model circuits; anda switching circuit coupled to the accurate and low power delay model circuits and configured to provide the delayed clock signal responsive to the accurate delay model circuit during initialization of the clock generation circuit and to, at some point thereafter, provide the delayed clock signal responsive to the low power delay model circuit.