| 摘要 |
PROBLEM TO BE SOLVED: To provide a frequency-locked loop circuit and a semiconductor integrated circuit mounted therewith which reduce deterministic jitter.SOLUTION: An FLL circuit 112 includes a digitally controlled oscillator 140 for generating a clock, and an FLL controller 120 for generating a frequency control code for controlling an oscillation frequency of the clock. The FLL controller 120 has a frequency comparison section 121 for comparing the frequency of the clock generated by the digitally controlled oscillator 140 with the frequency of a multiplied reference clock by the use of first and second thresholds, and a delay code controller 123 for generating the frequency control code such that the frequency of the clock generated by the digitally controlled oscillator 140 matches the frequency of the multiplied reference clock, on the basis of the result of comparison. The digitally controlled oscillator 140 adjusts the frequency of the generated clock according to the frequency control code. |
