INVERSE REQUEST AGGREGATION

摘要

A system and method for efficiently scheduling memory access requests from a display controller pipeline. The display controller monitors the amount of data in the line buffers in the internal pixel-processing pipelines. The display controller waits until the amount of data in a given line buffer has fallen below an amount equal to the pixel width of the region being rendered by the internal pixel-processing pipeline before issuing memory requests to the memory controller. When the memory controller is not processing received memory requests, the memory controller transitions to a low-power state.

主权项

1. An apparatus comprising:
a memory controller configured to control access to a memory; and a display controller comprising a display pipeline configured to read frame data stored in the memory for an image to be presented on a display; wherein after receiving frame data corresponding to a first plurality of memory requests, the display controller is configured to:
monitor an amount of frame data stored in a line buffer of a first internal pixel-processing pipeline of the display pipeline; andwait until less than a first amount of frame data is stored in the line buffer of the first internal pixel-processing pipeline prior to issuing memory requests from the first internal pixel-processing pipeline to the memory controller, wherein the first amount of frame data corresponds to a first number of pixels.