| 摘要 |
<p>A circuit includes a Static Random Access Memory (SRAM) array. An SRAM cell is in the SRAM array and includes a p-well region, a first and a second n-well region on opposite sides of the p-well region, and a first and a second pass-gate FinFET. The first pass-gate FinFET and the second pass-gate FinFET are p-type FinFETs. A CVss line is over the p-well region, wherein the CVss line is parallel to an interface between the p-well region and the first n-well region. A bit-line and a bit-line bar are on opposite sides of the CVss line. A CVdd line crosses over the SRAM cell. A CVss control circuit is connected to the CVss line. The CVss control circuit is configured to provide a first CVss voltage and a second CVss voltage to the CVss line, with the first and the second CVss voltage being different from each other.</p> |
