DATA WRITING METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROLLER

摘要

A data writing method, a memory storage device, and a memory controller for controlling a rewritable non-volatile memory module are provided. The rewritable non-volatile memory module includes at least one memory chip, and each memory chip includes a plurality of physical erasing units. The data writing method includes following steps. A data is written into at least one first physical erasing unit. A first error correction code and a second error correction code are respectively generated according to the data, where a number of bits correctable to the second error correction code is greater than a number of bits correctable to the first error correction code. The second error correction code is written into a second physical erasing unit. The first physical erasing unit and the second physical erasing unit belong to the same memory chip. Thereby, the memory space can be efficiently used.

主权项

1. A data writing method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises at least one memory chip, each of the at least one memory chip comprises a plurality of physical erasing units, each of the physical erasing units comprises a plurality of physical programming units, and the physical programming units of each of the physical erasing units comprise a plurality of fast physical programming units and a plurality of slow physical programming units, wherein a write speed of the fast physical programming units is faster than a write speed of the slow physical programming units, the data writing method comprising:
writing a first data only into at least one of the fast physical programming units; generating a first error correction code according to the first data, wherein the first error correction code is configured for correcting a part of bits in a single one of the fast physical programming units into which at least a part of the first data is written; generating a second error correction code according to the first data, wherein the second error correction code is configured for correcting the fast physical programming unit into which at least a part of the first data is written, and a number of bits correctable to the second error correction code is greater than a number of bits correctable to the first error correction code; writing the first error correction code and the second error correction code into at least one of the physical erasing units; writing a second data only into at least one of the slow physical programming units; generating a third error correction code according to the second data, wherein the third error correction code is configured for correcting a part of bits in a single one of the slow physical programming units into which at least a part of the second data is written; generating a fourth error correction code according to the second data, wherein the fourth error correction code is configured for correcting at least one of the slow physical programming units into which the second data is written, and a number of bits correctable to the fourth error correction code is greater than a number of bits correctable to the third error correction code; and writing the third error correction code and the fourth error correction code into at least one of the physical erasing units.