发明名称 |
OPTICAL WIRING SUBSTRATE, MANUFACTURING METHOD OF OPTICAL WIRING SUBSTRATE AND OPTICAL MODULE |
摘要 |
An optical wiring substrate includes a first conductor layer including a metal, a second conductor layer including a metal and arranged parallel to the first conductor layer, an insulation layer disposed to insulate the first conductor layer from the second conductor layer, and an electronic component including a photoelectric conversion element mounted on the substrate, and a via hole formed in the second conductor layer and the insulation layer so as to pass through the second conductor layer and the insulation layer in a thickness direction thereof, the via hole including an inner surface plated with a metal. The via hole is configured such that at least a part of a bottom surface thereof blocked by the first conductor layer is arranged in a plan view so as to overlap with an arrangement position of a pad of the electronic component that is mounted on the first conductor layer. |
申请公布号 |
US2014332978(A1) |
申请公布日期 |
2014.11.13 |
申请号 |
US201414250523 |
申请日期 |
2014.04.11 |
申请人 |
Hitachi Metals, Ltd. |
发明人 |
YASUDA Hiroki;HIRANO Kouki;ISHIKAWA Hiroshi |
分类号 |
H01L23/522;H01L21/768 |
主分类号 |
H01L23/522 |
代理机构 |
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代理人 |
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主权项 |
1. An optical wiring substrate, comprising:
a first conductor layer comprising a metal; a second conductor layer comprising a metal and arranged parallel to the first conductor layer; an insulation layer disposed to insulate the first conductor layer from the second conductor layer; and an electronic component including a photoelectric conversion element mounted on the substrate; and a via hole formed in the second conductor layer and the insulation layer so as to pass through the second conductor layer and the insulation layer in a thickness direction thereof, the via hole comprising an inner surface plated with a metal, wherein the via hole is configured such that at least a part of a bottom surface thereof blocked by the first conductor layer is arranged in a plan view so as to overlap with an arrangement position of a pad of the electronic component that is mounted on the first conductor layer. |
地址 |
Tokyo JP |