MULTICHIP INTEGRATION WITH THROUGH SILICON VIA (TSV) DIE EMBEDDED IN PACKAGE

摘要

Embodiments of the present disclosure are directed to integrated circuit (IC) package assemblies with three-dimensional (3D) integration of multiple dies, as well as corresponding fabrication methods and systems incorporating such 3D IC package assemblies. A bumpless build-up layer (BBUL) package substrate may be formed on a first die, such as a microprocessor die. Laser radiation may be used to form an opening in a die backside film to expose TSV pads on the back side of the first die. A second die, such as a memory die stack, may be coupled to the first die by die interconnects formed between corresponding TSVs of the first and second dies. Underfill material may be applied to fill some or all of any remaining gap between the first and second dies, and/or an encapsulant may be applied over the second die and/or package substrate. Other embodiments may be described and/or claimed.

主权项

1. A package assembly comprising:
a package substrate with a plurality of build-up layers; a first die embedded in the package substrate, the first die having a first side with one or more transistors, a second side opposite to the first side, a first through silicon via (TSV), and an electrical routing feature disposed on a first portion of the second side, wherein the electrical routing feature is electrically coupled with at least one transistor of the one or more transistors by the first TSV; an adhesive layer disposed on a second portion of the second side of the first die; and a second die coupled with the adhesive layer, the second die having a second TSV, wherein the second TSV is electrically coupled with the first TSV.