发明名称 半導体記憶装置、および欠陥セルテスト方法
摘要 <p>A semiconductor memory device simultaneously selects an object cell and a counter cell which connect with a common bit line, simultaneously activates sub-word lines of the object cell and the counter cell after predetermined levels are written in the object cell and the counter cell, simultaneously read data of the object cell and the counter cell from the common bit line, and hence, determines whether the object cell is normal or defective, based on a voltage level of the common bit line. Thereby, the defective cell in the semiconductor memory device can be reliably detected.</p>
申请公布号 JP5623688(B2) 申请公布日期 2014.11.12
申请号 JP20070280754 申请日期 2007.10.29
申请人 发明人
分类号 G11C29/12;G11C11/401 主分类号 G11C29/12
代理机构 代理人
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