发明名称 SoC DEVICE VERIFICATION MODEL USING MEMORY INTERFACE
摘要 <p>A system on a chip (SoC) device verification system comprises: an SoC device model including one or more IPs and a memory controller; an external IP verification model receiving an instruction from the SoC device model and verifying operation of the one or more IPs included in the SoC device model; and a bus select model selecting one of the external IP verification model and an external device in response to a memory control signal received from the memory controller of the SoC device model.</p>
申请公布号 KR101460665(B1) 申请公布日期 2014.11.12
申请号 KR20080069299 申请日期 2008.07.16
申请人 发明人
分类号 G06F12/00;G06F13/16;H04L9/00 主分类号 G06F12/00
代理机构 代理人
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