Phase locked loop (PLL) with multi-phase time-to-digital converter (TDC)

摘要

One or more techniques or systems for locking a phase locked loop (PLL) are provided herein. In some embodiments, a multi-phase time-to-digital converter (TDC) includes a first phase finder, a phase predictor, a second phase finder, and a phase switch. For example, the first phase finder is configured to generate a first fractional phase signal based on a multi-phase variable clock (CKV) signal. For example, the phase predictor is configured to generate a phase select (QSEL) signal or a multi-phase CKV select (CKVSEL) signal based on a frequency command word (FCW) signal or the multi-phase CKV signal. For example, the second phase finder is configured to generate a second fractional phase signal based on the CKVSEL signal or the QSEL signal. For example, the phase switch is configured to select the first or second fractional phase signal based on a phase error (PHE) signal.

主权项

1. A multi-phase time-to-digital converter (TDC) for a phase locked loop (PLL), comprising:
a phase predictor configured to generate a multi-phase variable clock select (CKVSEL) signal based on at least one of a multi-phase variable clock (CKV) signal or a phase select (QSEL) signal; a phase finder configured to generate a fractional phase signal of the multi-phase CKV signal based on at least one of the CKVSEL signal or the QSEL signal; and a phase switch configured to generate a fractional variable phase correction (PHVF) signal based on the fractional phase signal when a phase error (PHE) signal applied to the phase switch is greater than a first threshold.