Input/output device power reduction and optimization by enablement or disablement of an external circuit coupled to the input/output device

摘要

Embodiments of the present invention provide a processor design that enables controller and I/O device power reduction and optimization. In a typical embodiment, a processing core is coupled to a set (e.g., three) of I/O blocks. The processing core provides for selective activation and/or deactivation of any of the I/O blocks. Two of the I/O blocks are coupled to individual voltage I/O components as well as individual external circuits. In one embodiment, the individual external circuits are coupled to individual voltage control components.

主权项

1. A processor, comprising:
a processing core; a set of input/output (I/O) blocks coupled to the processing core that perform I/O functions for the processing core, the set of I/O blocks comprising a first I/O block, a second I/O block, and a third I/O block, the set of I/O blocks being selectively activated and deactivated by the processing core, the processing core executing instructions to perform basic operations of the processor; a set of external circuits coupled to the set of I/O blocks, the set of external circuits comprising a first external circuit and a second external circuit, the first external circuit and the second external circuit each receiving an enablement signal and a control signal from the first I/O block; and a set of voltage I/O components coupled to the set of I/O blocks for providing power-performance optimization when the set of I/O blocks are activated.