发明名称 |
Semiconductor device |
摘要 |
A semiconductor device which includes a gate electrode electrically connected to a gate portion made of a polysilicon film provided inside of a plurality of grooves formed in a striped form along a direction of a chip region. The gate electrode is formed as a film at the same layer level as a source electrode electrically connected to a source region formed between adjacent stripe-shaped grooves. The gate electrode is constituted of a gate electrode portion formed along a periphery of the chip region and a gate finger portion arranged to divide the chip region into halves. The source electrode is constituted of an upper portion and a lower portion relative to the gate finger portion, and the gate electrode and the source electrode are connected to a lead frame via a bump electrode. |
申请公布号 |
US8884361(B2) |
申请公布日期 |
2014.11.11 |
申请号 |
US201213350438 |
申请日期 |
2012.01.13 |
申请人 |
Renesas Electronics Corporation |
发明人 |
Shirai Nobuyuki;Matsuura Nobuyoshi |
分类号 |
H01L29/76;H01L29/78;H01L29/66;H01L29/423;H01L29/45;H01L29/417;H01L29/06;H01L29/49 |
主分类号 |
H01L29/76 |
代理机构 |
Miles & Stockbridge P.C. |
代理人 |
Miles & Stockbridge P.C. |
主权项 |
1. A semiconductor device comprising:
a power MISFET in a first region of a semiconductor substrate and having
a gate comprised of a first conductor;a source; anda drain; a gate electrode over the gate, electrically coupled to the gate, comprised of a second conductor whose resistivity is lower than that of the first conductor, and having a gate finger portion; a source electrode over the source, electrically coupled to the source, comprised of the second conductor, and having a plurality of regions; a drain electrode over the drain and electrically coupled to the drain of the power MISFET; a gate bump electrode over the gate electrode and electrically coupled to the gate of the power MISFET; a plurality of source bump electrodes over each of the respective plurality of regions of the source electrode; a gate lead over the gate bump electrode and electrically coupled to the gate bump electrode; a source lead over the source bump electrodes and electrically coupled to the plurality of source bump electrodes; a drain lead over the drain electrode and electrically coupled to the drain electrode; and a resin body sealing the semiconductor substrate, wherein the gate electrode and the source electrode are formed in a same conductive layer, and wherein the gate finger portion of the gate electrode is located between two adjacent regions of the plurality of regions of the source electrode. |
地址 |
Kawasaki-shi JP |