发明名称 |
Memory device and method for manufacturing the same |
摘要 |
According to one embodiment, a memory device includes: a first signal line; a second signal line; a transistor; a memory region; and a conductive region. The transistor controls a conduction of each of a current in a first direction flowing between the first line and the second line and a current in a second direction opposite to the first direction. The memory region has a first magnetic tunnel junction element which is connected between the first line and one end of the transistor, a magnetization direction of which becomes parallel when a current not less than a first parallel threshold value flows in the first direction, and the magnetization direction of which becomes antiparallel when a current not less than a first antiparallel threshold value flows in the second direction. The conductive region is connected between the second line and the other end of the transistor. |
申请公布号 |
US8885396(B2) |
申请公布日期 |
2014.11.11 |
申请号 |
US201213423973 |
申请日期 |
2012.03.19 |
申请人 |
Kabushiki Kaisha Toshiba |
发明人 |
Yamanaka Takaya;Shuto Susumu |
分类号 |
G11C11/00;H01L43/08;H01L27/22;G11C11/16 |
主分类号 |
G11C11/00 |
代理机构 |
Knobbe, Martens, Olson & Bear LLP |
代理人 |
Knobbe, Martens, Olson & Bear LLP |
主权项 |
1. A memory device comprising:
a first signal line; a second signal line; a transistor configured to control a conduction of each of a current in a first direction flowing between the first signal line and the second signal line and a current in a second direction opposite to the first direction; a memory region having a first magnetic tunnel junction element which is connected between the first signal line and one end of the transistor, a magnetization direction of which becomes parallel when a current not less than a first parallel threshold value flows in the first direction, and the magnetization direction of which becomes antiparallel when a current not less than a first antiparallel threshold value flows in the second direction; and a conductive region connected between the second signal line and the other end of the transistor. |
地址 |
Tokyo JP |