发明名称 Semiconductor device
摘要 The present invention has an object of providing a high-speed, low-cost, and user-friendly information processing system that can ensure scalability of memory capacity. The information processing system is configured to include an information processing device, a volatile memory, and a nonvolatile memory. By serially connecting the information processing device, the volatile memory, and the nonvolatile memory and reducing the number of connection signals, processing speed is increased while maintaining the scalability of memory capacity. When transferring data of the nonvolatile memory to the volatile memory, error correction is performed, thereby improving reliability. The information processing system including the plurality of chips is configured as an information-processing system module in which the chips are alternately stacked and arranged, and wired by a ball grid array (BGA) or by bonding between the chips.
申请公布号 US8886893(B2) 申请公布日期 2014.11.11
申请号 US200812597097 申请日期 2008.04.25
申请人 PS4 Luxco S.a.r.l. 发明人 Miura Seiji;Haraguchi Yoshinori;Abe Kazuhiko;Kaneko Shoji
分类号 G06F12/00;G11C7/00;G06F13/42 主分类号 G06F12/00
代理机构 Sughrue Mion, PLLC 代理人 Sughrue Mion, PLLC
主权项 1. A semiconductor device comprising a request interface circuit and a response interface circuit, wherein the request interface circuit has a plurality of request queues, the response interface circuit has a plurality of response queues, and the request interface circuit receives a request including (i) a queue reservation instruction for reserving one or more request queues from among the plurality of request queues and one or more response queues from among the plurality of response queues and (ii) a number of queues to be reserved, wherein the semiconductor device includes a plurality of serially connected memory devices, and each of the plurality of memory devices (i) includes the request interface circuit and the response interface circuit, (ii) has a respective plurality of request queues for transmitting and receiving requests and a respective plurality of response queues for transmitting and receiving responses, (iii) receives the request, (iv) has an ID register for storing an ID number of the memory devices, and (v) has a comparison circuit for comparing a value of the request to the ID number of the memory devices.
地址 Luxembourg LU