发明名称 Radiation hard and fault tolerant multicore processor and method for ionizing radiation environment
摘要 A redundancy system in a fault tolerant computer comprises a multiple core processor which may support a real time operating system. The multiple core machine may be actual or virtual. Multiple identical instructions, e.g., three instructions, are executed redundantly so that the redundancy system can detect and recover from a single event upset (SEU). The instructions are also displaced in time. In one form, two non-consecutive instructions are run on one core which is virtualized into two cores. Alternatively, a second actual core may provide symmetric processing. The system prevents single event functional interrupts (SEFIs) from hanging up the processor. Each core may run a separate operating system. When a first core hangs up a first operating system, the second operating system takes over operation and the processor recovers. Embedded routines may store selected data variables in memory for later recovery and perform an SEFI “self-test” routine.
申请公布号 US8886994(B2) 申请公布日期 2014.11.11
申请号 US201012928084 申请日期 2010.12.03
申请人 Space Micro, Inc. 发明人 Czajkowski David R.
分类号 G06F11/00;G06F11/16;G06F11/14;G06F11/18 主分类号 G06F11/00
代理机构 Continuum Law 代理人 Continuum Law ;Cogan Robert P.
主权项 1. A redundancy system in a fault tolerant computer comprising: a processor having at least two cores to execute instructions, at least two operating systems each running on one of said at least two cores and each providing a separate software thread, said processor including instructions to execute first and second identical instructions to the processor to produce first and second respective results to be compared in a redundancy routine, said compared results being produced during separate time periods, a comparison command executed in one of said cores, said comparison providing an output indicative of equality or inequality of said first and second results, an indication of inequality comprising an SEU error signal, and producing a third instruction signal coupled for voting in one of said cores in response to an SEU error signal, said processor having a real time operating system and a processing rate of at least one gigahertz.
地址 San Diego CA US
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