Stereoscopic image display

摘要

A stereoscopic image display is discussed. The stereoscopic image display includes a display panel including data lines, gate lines crossing the data lines, thin film transistors (TFTs) that are turned on in response to gate pulses from the gate lines, and a plurality of pixels, a data driving circuit that converts digital video data into a data voltage and supplies the data voltage to the data lines, a gate driving circuit sequentially supplying the gate pulses synchronized with the data voltage to the gate lines, and a timing controller that receives a timing signal, 2D image data, and 3D image data from an external host system, supplies the digital video data to the data driving circuit, and controls an operation timing of the data driving circuit and an operation timing of the gate driving circuit.

主权项

1. A stereoscopic image display comprising:
a display panel including data lines, gate lines crossing the data lines, thin film transistors (TFTs) that are turned on in response to gate pulses from the gate lines, and a plurality of pixels each including a plurality of subpixels; a data driving circuit configured to convert digital video data into a data voltage and supply the data voltage to the data lines; a gate driving circuit configured to sequentially supply the gate pulses synchronized with the data voltage to the gate lines; and a timing controller configured to receive a timing signal, 2D image data, and 3D image data from an external host system, supply the digital video data to the data driving circuit, and control an operation timing of the data driving circuit and an operation timing of the gate driving circuit, wherein each subpixel includes: a main pixel part configured to represent a gray level of the 2D image data in response to an n-th gate pulse from an n-th gate line in a 2D mode and represent a gray level of the 3D image data in response to the n-th gate pulse in a 3D mode, where n is a natural number; and a subpixel part configured to discharge a previously charged voltage in response to an (n+1)-th gate pulse from an (n+1)-th gate line in the 3D mode and represent a black gray level, wherein the gate driving circuit outputs the n-th gate pulse and does not output the (n+1)-th gate pulse in the 2D mode, and outputs the n-th gate pulse and the (n+1)-th gate pulse in the 3D mode in response to a selection signal received from the timing controller or the host system.