Clock generator

摘要

Disclosed herein is a device comprising a first terminal for a first clock signal, a second terminal for a second clock signal substantially complementary to the first clock signal, a third terminal for a third clock signal, a fourth terminal for a fourth clock signal substantially complementary to the third clock signal, a first logic gate to produce a first intermediate signal, a second logic gate to produce a second intermediate signal, a first delay circuit to produce a third intermediate signal, and a second delay circuit to produce a fourth intermediate signal, and a first output circuit coupled to the first and second delay circuits to produce the third and fourth clock signals respectively at the third and fourth terminals.

主权项

1. A device comprising:
a first terminal for a first clock signal: a second terminal for a second clock signal that is substantially complementary to the first clock signal; a third terminal for a third clock signal; a fourth terminal for a fourth clock signal that is substantially complementary to the third clock signal; a first logic gate performing a first logic operation on the first and third clock signals to produce a first intermediate signal; a second logic gate performing a second logic operation on the second and fourth clock signals to produce a second intermediate signal; a first delay circuit delaying the first intermediate signal to produce a third intermediate signal; a second delay circuit delaying the second intermediate signal to produce a fourth intermediate signal; and a first output circuit coupled to the first and second delay circuits to produce the third and fourth clock signals respectively at the third and fourth terminals.