Vertical memory cells and methods, architectures and devices for the same

摘要

A memory device may include a plurality of cell pairs each including insulator regions interposed between opposing sides of at least one common word line gate and first and second vertical sides formed by a spacing within at least one semiconductor material; and at least one selector gate vertically aligned with the word line gate within the spacing configured to enable first and second source regions in the first and second vertical sides, respectively; wherein when the selector gate is enabled, the first and second source regions are connected to different source diffusion regions.

主权项

1. A memory device, comprising:
a plurality of cell pairs including insulator regions interposed between opposing sides of a plurality of word line gates and first and second vertical sides formed by a spacing within at least one semiconductor material; and at least one selector gate vertically aligned with the word line gates within the spacing configured to enable first and second source regions in the first and second vertical sides, respectively; and a controller electrically coupled to the first and second source regions configured to drive the first and second source regions to different bias states; wherein when the selector gate is enabled, the first and second source regions are connected to different source diffusion regions by inverting portions of the first and second vertical sides to create first type conductivity regions within a second conductivity type substrate.