Frequency lock loop for hysteretic switching regulators

摘要

Embodiments of the present invention provide systems and methods for reducing switching frequency variation in a hysteretic switching regulator. Embodiments of the present invention provide a new duty cycle controller for a switching regulator incorporating a new Frequency Lock Loop (FLL) for controlling the hysteresis of a comparator, and this hysteresis variation directly controls the switching frequency. The FLL of the present invention advantageously maintains a fixed frequency operation for a switching regulator while not affecting the transient response or stability of the main loop because it only changes the hysteresis of the fast comparator and does not introduce delays in the main loop of the switching regulator. Thus, the FLL of the present invention advantageously maintains a fixed switching frequency while causing a minimal impact to the switching regulator.

主权项

1. A voltage regulator, comprising:
a first switch; a hysteretic comparator coupled to an output of the first switch, wherein the hysteretic comparator is configured to generate a duty signal; and a Frequency Lock Loop (FLL), comprising:
a delay module,a second switch coupled to the delay module,a first current source coupled to the second switch, anda second current source coupled to the second switch, wherein the first current source is configured to be larger than the second current source, wherein the FLL is coupled to a control input of the hysteretic comparator, and wherein the FLL is configured to:receive the duty signal,adjust a width of a pulse generated by the delay module based on a target switching frequency of the hysteretic comparator and a ratio of current between the first current source and the second current source, andgenerate, based on the pulse, a signal to alter a hysteresis of the hysteretic comparator such that a switching frequency of the first switch is maintained at the target switching frequency.