发明名称 |
Nonvolatile semiconductor memory device |
摘要 |
A nonvolatile semiconductor memory device of an embodiment includes a p-type semiconductor substrate, a first P-well formed in the semiconductor substrate, and on which a plurality of memory cells is formed, an first N-well surrounding the first P-well and electrically separating the first P-well from the semiconductor substrate, a first negative voltage generation unit configured to generate a first negative voltage, a boost unit configured to boost a voltage and generate a boosted voltage, and a well voltage transmission unit connected to the first negative voltage generation unit, the boost unit, and the first P-well, and configured to switch a voltage between the first negative voltage and the boosted voltage, the voltage being applied to the first P-well. |
申请公布号 |
US8885414(B2) |
申请公布日期 |
2014.11.11 |
申请号 |
US201213602738 |
申请日期 |
2012.09.04 |
申请人 |
Kabushiki Kaisha Tosiba |
发明人 |
Kutsukake Hiroyuki |
分类号 |
G11C11/34;G11C16/30;G11C16/10;H01L27/115;G11C16/16;G11C16/04 |
主分类号 |
G11C11/34 |
代理机构 |
Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P. |
代理人 |
Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P. |
主权项 |
1. A nonvolatile semiconductor memory device comprising:
a p-type semiconductor substrate; a first P-well formed in the semiconductor substrate, a plurality of memory cells being formed on the first P-well; a first N-well surrounding the first P-well, the first N-well electrically separating the first P-well from the semiconductor substrate; a first negative voltage generation unit configured to generate a first negative voltage; a boost unit configured to boost a voltage and generate a boosted voltage; a well voltage transmission unit connected to the first negative voltage generation unit, the boost unit, and the first P-well, the well voltage transmission unit configured to switch a voltage being applied to the first P-well between the first negative voltage and the boosted voltage; a second P-well formed in the semiconductor substrate, a bit line connection transistor connecting a bit line of the memory cells and a sense amplifier unit being formed on the second P-well; and a second N-well surrounding the second P-well, the second N-well electrically separating the second P-well from the semiconductor substrate. |
地址 |
Tokyo JP |