Compensation scheme for non-volatile memory

摘要

Methods for performing parallel voltage and current compensation during reading and/or writing of memory cells in a memory array are described. In some embodiments, the compensation may include adjusting a bit line voltage and/or bit line reference current applied to a memory cell based on a memory array zone, a bit line layer, and a memory cell direction associated with the memory cell. The compensation may include adjusting the bit line voltage and/or bit line reference current on a per memory cell basis depending on memory cell specific characteristics. In some embodiments, a read/write circuit for reading and/or writing a memory cell may select a bit line voltage from a plurality of bit line voltage options to be applied to the memory cell based on whether the memory cell has been characterized as a strong, weak, or typical memory cell.

主权项

1. A method for operating a non-volatile storage system, comprising:
generating a plurality of bit line voltage options associated with a programming operation; determining a state associated with a memory cell; determining an upper current threshold based on the state; determining a first control bit based on whether an output current associated with the memory cell is greater than the upper current threshold; selecting a first bit line voltage of the plurality of bit line voltage options based on the first control bit; and programming the memory cell by applying the first bit line voltage to the memory cell.