Semiconductor device and semiconductor memory device including transistor and capacitor

摘要

A memory circuit is included. The memory circuit includes n field-effect transistors (n is a natural number of 2 or more) and n capacitors each including a pair of electrodes. A digital data signal is input to one of a source and a drain of the first field-effect transistor. One of a source and a drain of the k-th field-effect transistor (k is a natural number of greater than or equal to 2 and less than or equal to n) is electrically connected to the other of a source and a drain of the (k−1)-th field-effect transistor. One of the pair of electrodes of the m-th capacitor (m is a natural number of n or less) is electrically connected to the other of a source and a drain of the m-th field-effect transistor of the n field-effect transistors. At least two of the n capacitors have different capacitance values.

主权项

1. A semiconductor device comprising:
a memory circuit, wherein the memory circuit comprises:
n field-effect transistors (n is a natural number of 2 or more) in a first group;n capacitors each including a pair of electrodes; anda field-effect transistor in a second group, wherein a digital data signal is input to one of source and drain of a first field-effect transistor of the n field-effect transistors in the first group, wherein one of source and drain of a second field-effect transistor of the n field-effect transistors in the first group is electrically connected to the other of source and drain of the first field-effect transistor of the n field-effect transistors in the first group, wherein one of the pair of electrodes of a first capacitor of the n capacitors is electrically connected to the other of source and drain of the first field-effect transistor of the n field-effect transistors in the first group and the other of the pair of electrodes of the first capacitor of the n capacitors is electrically connected to a wiring, wherein one of the pair of electrodes of a second capacitor of the n capacitors is electrically connected to the other of source and drain of the second field-effect transistor of the n field-effect transistors in the first group and the other of the pair of electrodes of the second capacitor of the n capacitors is electrically connected to the wiring, and wherein a gate of the field-effect transistor in the second group is electrically connected to the other of source and drain of an n-th field-effect transistor in the first group.