发明名称 PARTIAL BLOCK ERASE ARCHITECTURE FOR FLASH MEMORY
摘要 <p>A method and system for increasing the lifespan of a flash memory device by selectively erasing sub-blocks of a memory block. Each physical memory block of the flash memory device is dividable into at least two logical sub-block, where each of the at least two logical sub-blocks is erasable. Therefore, only the data of the logical sub-block is erased and reprogrammed while unmodified data in the other logical sub-block avoids unnecessary program/erase cycles. The logical sub-blocks to be erased are dynamically configurable in size and location within the block. A wear leveling algorithm is used for distributing data throughout the physical and logical sub-blocks of the memory array to maximize the lifespan of the physical block during programming and data modification operations.</p>
申请公布号 KR101460826(B1) 申请公布日期 2014.11.11
申请号 KR20097020969 申请日期 2008.03.04
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分类号 G11C16/02;G11C16/08;G11C16/14;G11C16/16 主分类号 G11C16/02
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