CHIP PACKAGE AND METHOD FOR FORMING THE SAME

摘要

An embodiment of the invention provides a chip package which includes: a carrier substrate; a semiconductor substrate having an upper surface and a lower surface, disposed overlying the carrier substrate; a device region or sensing region located on the upper surface of the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.

主权项

1. A chip package, comprising:
a substrate having an upper surface and a lower surface; a recess adjacent to a sidewall of the substrate, wherein the recess is formed along a direction from the upper surface toward the lower surface of the substrate; a device region or sensing region of biological features located on the upper surface of the substrate; a conducting pad located on the upper surface of the substrate; and a conducting layer electrically connected to the conducting pad and extending to the recess along the sidewall of the substrate.