| 摘要 |
A thin semiconductor wafer, on which a top surface structure and a bottom surface structure that form a semiconductor chip are formed, is affixed to a supporting substrate by a double-sided adhesive tape. Then, on the thin semiconductor wafer, a trench to become a scribing line is formed by wet anisotropic etching with a crystal face exposed so as to form a side wall of the trench. On the side wall of the trench with the crystal face thus exposed, an isolation layer for holding a reverse breakdown voltage is formed by ion implantation and low temperature annealing or laser annealing so as to be extended to the top surface side while being in contact with a p collector region as a bottom surface diffused layer. Then, laser dicing is carried out to neatly dice a collector electrode, formed on the p collector region, together with the p collector region, without presenting any excessive portions and any insufficient portions under the isolation layer. Thereafter, the double-sided adhesive tape is removed from the collector electrode to produce semiconductor chips. A highly reliable reverse-blocking semiconductor device can thus be formed at a low cost. |
| 主权项 |
1. A semiconductor device comprising:
a second conductivity type base region selectively provided in a surface region on a first principal surface of a first conductivity type semiconductor substrate; a first conductivity type emitter region selectively provided in a surface region on the base region; a MOS gate structure including: a gate insulator film provided on a surface of a section of the base region, the section being positioned between the semiconductor substrate and the emitter region; and a gate electrode provided on the gate insulator film; an emitter electrode in contact with the emitter region and the base region; a second conductivity type collector layer provided on a surface layer of a second principal surface of the semiconductor substrate; a collector electrode in contact with the collector layer; and a second conductivity type isolation layer surrounding the MOS gate structure, reaching the second principal surface from the first principal surface while being inclined to the second principal surface, and being coupled to the collector layer, each of the first principal surface and the second principal surface being a {100} plane, and the isolation layer being an impurity layer formed by introducing a second conductivity type impurity into a side wall of a {111} plane of a trench formed in the semiconductor substrate. |
