| 主权项 |
1. A multi-threaded processor system, comprising:
a plurality of data processing cores capable of being configured to simultaneously execute multiple threads for a program on multiple of the plurality of data processing cores; an instruction decode unit configured to decode instructions from the program, to be used to configure the multiple data processing cores, and to generate an indication when a thread that is executing instructions from the program, which is to be synchronized with other threads of the multiple threads, branches around a section of program instructions, while the other threads do not; and a control core coupled with the instruction decode unit to receive the indication and to control which threads are to execute on which of the plurality of data processing cores, the control core comprising non-transitory memory containing status data for a plurality of threads, of which the multiple threads are a subset,
wherein a number of threads in the plurality of threads is greater than a number of the multiple threads, and the status data comprises, for each of the subset of the plurality of threads, an indication whether that thread is waiting to be synchronized andthe control core is responsive to receiving the indication, by updating the status data for the thread to which the indication pertains, and to swap a thread from the plurality of threads to be executed by the plurality of data processing cores, which is not waiting for synchronization with any other thread of the plurality of threads. |
