| 摘要 |
<p>PROBLEM TO BE SOLVED: To reduce access frequency to a main memory unit at cache miss.SOLUTION: When a replacement occurs on a line within a cache memory due to a cache miss happened while attempting to make access to a predetermined address in a main memory unit, in a data for one line stored on a replacement target line, a data stored in an entry offset corresponding to the predetermined address of the main memory unit, to which the access is attested to be made, is stored while being associated with other predetermined address of the main memory unit as an address corresponding to the data. When other cache miss occurs while loading and when the address, to which access is attempted in the other cache miss, is identical to the other predetermined address of the main memory unit, the data stored being associated with the other predetermined address is determined as a loading data.</p> |
