ANALYZING SPARSE WIRING AREAS OF AN INTEGRATED CIRCUIT DESIGN

摘要

A set of nets in an integrated circuit design, having a timing margin and traverse routing tiles, are identified. The set of nets are assigned a utilization metric based on the traversed routing tiles. A set of sparse nets are determined from the set of nets, based on the utilization metric of each net in the set of sparse nets. One or more target nets are selected from the set of sparse nets, based on the timing margin of the target nets. The target nets may be modified.

主权项

1. A method of analyzing an integrated circuit design arranged into a grid of routing tiles, the method comprising:
accessing memory for a netlist of the integrated circuit design; identifying a set of nets that traverse a set of routing tiles of the integrated circuit design, each net traversing at least one routing tile; identifying a set of timing margins for the set of nets, each net having at least one timing margin; identifying a set of congestion metrics for the set of routing tiles, each routing tile having at least one congestion metric, assigning, the set of nets a set of utilization metrics based on the set of congestion metrics, each net having at least one utilization metric; determining a set of sparse nets from the set of nets based on the set of utilization metric; selecting one or more target nets from the set of sparse nets based on the set of timing margins; increasing, for the one or more target nets, at least one timing margin from the set of timing margins by modifying a wire code of the one or more target nets; and storing the wire code of the one or more target nets in the memory.