| 摘要 |
<p>Provided are a VLSI tamper-evident architecture that generates a fingerprint for the sequence of internal states of a hardware system during the performance of a computation, and a VLSI tamper detection method that verifies the generated fingerprints offline based on re-computation on a different implementation of the same hardware system, and a VLSI system including an ASIC circuit and a reconfigurable circuit that obfuscates the ASIC circuit.</p> |
