| 摘要 |
A modulation processor (500) comprises a first processing stage (110) and a second processing stage (120). The first processing stage (110) comprises a phase generation stage (117) arranged to generate a phase signal (PM) indicative of a phase of a modulation signal (S), a differentiation stage (118) arranged to generate a frequency signal (FM) by differentiating the phase signal (PM), and a first bandwidth reduction stage (113) arranged to generate a first output signal (FM_LP) by reducing a bandwidth of the frequency signal (FM). The second processing stage (120) is arranged to generate a second output signal (AM*) proportional to the modulation signal (S) with its phase retarded by an angle equal to an integral of the first output signal (FM_LP). |
