Low power, high performance, heterogeneous, scalable processor architecture

摘要

One embodiment of the present includes a heterogeneous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value smaller than W by a factor of two. The processor further includes a shared bus coupling the at least one W-type sub-processor and at least one N-type sub-processor and memory shared coupled to the at least one W-type sub-processor and the at least one N-type sub-processor, wherein the W-type sub-processor rearranges memory to accommodate execution of applications allowing for fast operations.

主权项

1. A heterogeneous, scalable processor, said processor comprising:
a first heterogeneous programmable integrated circuit sub-processor configured for 16, 24, 32 and 64-bit processing; a second heterogeneous programmable integrated circuit sub-processor configured for 1, 4 and 8-bit processing; and a shared bus coupled to the first and second sub-processors, wherein at least one of the first and second sub-processors include one or more functional units each including a memory and configured for rearrangement of data values to and from the memory, and wherein each of the first and second sub-processors can only execute one function at a time with an internal control block configured to synchronize an order of function execution.