Soft erase operation for 3D non-volatile memory with selective inhibiting of passed bits

摘要

An erase operation for a 3D stacked memory device selectively inhibits subsets of memory cells which meet a verify condition as the erase operation progresses. As a result, the faster-erasing memory cells are less likely to be over-erased and degradation is reduced. Each subset of memory cells can be independently erased by controlling a select gate, drain (SGD) transistor line, a bit line or a word line, according to the type of subset. For a SGD line subset or a bit line subset, the SGD line or bit line, respectively, is set at a level which inhibits erase. For a word line subset, the word line voltage is floated to inhibit erase. An inhibit or uninhibit status can be maintained for each subset, and each type of subset can have a different maximum allowable number of fail bits.

主权项

1. A three-dimensional non-volatile memory device, comprising:
a plurality of word lines comprising conductive material, the conductive material alternates with dielectric material in a stack; a plurality of memory cells arranged in a plurality of NAND strings, each NAND string comprising a select gate drain (SGD) transistor at a drain-side end of the NAND string; a set of bit lines in communication with the drain-side ends of the NAND strings; a set of SGD lines in communication with the SGD transistors of the NAND strings; and a control circuit, the control circuit:
performs one erase iteration of an erase operation for the plurality of memory cells in which the plurality of memory cells is not inhibited from being erased, and after the one erase iteration, performs a verify test using a first verify condition, the verify test using the first verify condition is passed by a first subset of memory cells in the plurality of memory cells and is not passed by second and third subsets of memory cells in the plurality of memory cells;performs another erase iteration of the erase operation in which the first subset of memory cells is inhibited from being erased while the second and third subsets of memory cells are not inhibited from being erased, and after the another erase iteration, performs a verify test using a second verify condition, the verify test using the second verify condition is passed by the second subset of memory cells but not by the third subset of memory cells; andperforms an additional erase iteration of the erase operation in which the first and second subsets of memory cells are inhibited from being erased while the third subset of memory cells is not inhibited from being erased, and after the additional erase iteration, performs a verify test using a third verify condition, the verify test using the third verify condition is passed by the third subset of memory cells.