发明名称 Method and algorithm for random half pitched interconnect layout with constant spacing
摘要 An embodiment of a system and method produces a random half pitched interconnect layout. A first normal-pitch mask and a second normal-pitch mask are created from a metallization layout having random metal shapes. The lines and spaces of the first mask are printed at normal pitch and then the lines are shrunk to half pitch on mask material. First spacers are used to generate a half pitch dimension along the outside of the lines of the first mask. The mask material outside of the first spacer pattern is partially removed. The spacers are removed and the process is repeated with the second mask. The mask material remains at the locations of first set of spacers and/or the second set of spacers to create a half pitch interconnect mask with constant spaces.
申请公布号 US8877639(B2) 申请公布日期 2014.11.04
申请号 US201213433086 申请日期 2012.03.28
申请人 Micron Technology, Inc. 发明人 Juengling Werner
分类号 H01L21/44;H01L21/033;G03F1/00;H01L21/768;H01L27/02 主分类号 H01L21/44
代理机构 Knobbe Martens Olson & Bear LLP 代理人 Knobbe Martens Olson & Bear LLP
主权项 1. A method of creating a half pitch interconnect from a half pitch interconnect layout comprising: generating a half pitched interconnect layout comprising a plurality of shapes in the plane of the interconnect layout, wherein the plurality of shapes include a plurality of shape designations, each shape designation having different shapes and shapes of the same designation are not adjacent in the plane of the interconnect layout; creating a first photo mask containing shapes having two or more of the plurality of shape designations; creating a second photo mask containing shapes having one or more of the plurality of shape designations included in the first photo mask and one or more of the plurality of shape designations not included in the first photo mask, wherein the first and second photo masks are dimensioned so that the first and second photo masks generate a half pitch interconnect corresponding to the half pitch interconnect layout when the first and second photo masks are used in a patterning process.
地址 Boise ID US