Decision feedback equalizer and transceiver

摘要

A decision feedback equalizer, transceiver, and method are provided, the equalizer having at least one comparator, the at least one comparator comprising a first stage, comprising a main branch having two track switches with a resistive load, an offset cancellation branch, a plurality of tap branches with transistor sizes smaller than the main branch, in which previous decisions of the equalizer are mixed with the tap weights using current-mode switching, and a cross coupled latch branch; and a second stage, comprising a comparator module for making decisions based on the outputs of the first stage and a clock input, and a plurality of flip-flops for storing the output of the comparator module.

主权项

1. A method for adapting an equalizer having a plurality of taps spaced sequentially at periods of one clock unit for observing a digital data system response produced by a digital system, comprising:
applying an arbitrary digital data sequence to the digital system; detecting a first predetermined digital data pattern in the data sequence; calculating a first error signal for a first tap of the plurality of taps based on the system response to the first data pattern; using the first error signal to adapt the first tap; and repeating the steps of detecting, calculating, and adapting for each tap other than the first tap in the plurality of taps,wherein:
the digital data pattern used in conjunction with a given tap at position k in the plurality of taps has equal symbol values at positions (m−k) and (m−k−1) and different symbol values at positions (m−p) and (m−p−1), where p is not equal to k, for some value of m, thereby comprising a digital data pattern having a lone bit; and the error signal calculated for the tap at sequential position k is proportional to the sum of the values of the system response measured at zero crossings directly before and after the lone bit of the digital data pattern.