发明名称 Accurate bias tracking for process variation and supply modulation
摘要 A current mirror includes a bias branch, which includes first and second transistors in series between a voltage source and ground, a voltage divider coupled between the voltage source and ground, an op-amp configured to receive a divided voltage of the voltage divider and a voltage of a node between the first and second transistors, and drive a gate of the second transistor to pull the node to the divided voltage. The current mirror further includes a power amplifier core coupled to the bias branch. The power amplifier core includes first and second drive transistors configured in series between the voltage source and ground. Gates of the first transistor and the first drive transistor are coupled, and gates of the second transistor and the second drive transistor are coupled.
申请公布号 US8878612(B2) 申请公布日期 2014.11.04
申请号 US201313944608 申请日期 2013.07.17
申请人 Marvell World Trade Ltd. 发明人 Leong Poh Boon;Krishnasamy Maniam Nuntha Kumar
分类号 H03F3/04;H03F3/24;H03F3/193;H03F3/16;G05F3/26;H03F3/45 主分类号 H03F3/04
代理机构 代理人
主权项 1. A circuit method for controlling node voltages of a current mirror comprising: receiving, by an op-amp of a bias branch, a divided voltage of a voltage divider and a voltage of a node between first and second transistors, wherein the first and second transistors are configured in series between a voltage source and a ground, and wherein the voltage divider is coupled between the voltage source and the ground; and driving, by the op-amp, a gate of the second transistor to pull the node to the divided voltage, wherein a power amplifier core is coupled to the bias branch, the power amplifier core including third and fourth transistors configured in series between the voltage source and the ground, wherein a gate of the first transistor and a gate of the third transistor are coupled, and the gate of the second transistor and a gate of the fourth transistor are coupled.
地址 St. Michael BB