System and method for scaling power of a phase-locked loop architecture

摘要

Apparatuses, systems, and a method for providing a PLL architecture with scalable power are described. In one embodiment, a system includes one or more processing units having a voltage regulator to generate a controllably adjustable supply voltage for a phase-locked loop (PLL) circuit coupled to the voltage regulator. The PLL circuit compares a phase and frequency of the reference clock signal to a phase and frequency of a generated feedback clock signal and generates an output signal based on the comparison. A tracking unit adjusts the controllably adjustable supply voltage based on an operating frequency of the system.

主权项

1. A system, comprising:
one or more processing units, comprising, a voltage regulator to generate a controllably adjustable supply voltage; a phase-locked loop (PLL) circuit coupled to the voltage regulator, the PLL circuit to receive the controllably adjustable supply voltage from the voltage regulator, to compare a phase and frequency of a reference clock signal to a phase and frequency of a generated feedback clock signal, and to generate an output signal based on the comparison; and a tracking unit to adjust the controllably adjustable supply voltage based on an operating frequency of the system.