Error detection method and a system including one or more memory devices

摘要

A system including one or more memory devices, and an error detection and correction method are disclosed. A memory device of the system includes an input for receiving a packet. A first portion of the packet may include at least one command byte, and a second portion of the packet may include parity bits to facilitate command error detection. The memory device may include an error manager configured to detect, based on the parity bits, whether an error exists in the at least one command byte, and circuitry configured to provide the packet to the error manager.

主权项

1. A system comprising:
a plurality of serially interconnected semiconductor memory devices arranged in a point-to-point ring topology; and a controller device to communicate with the semiconductor memory devices, the controller device comprising: a command engine to generate a memory device-destined packet, a portion of the packet comprising at least one command byte; an output to output the packet to a first device of the plurality of semiconductor memory devices; an input to receive the packet from a last device of the plurality of semiconductor memory devices after having been communicated through each of the plurality of semiconductor memory devices arranged in the point-to-point ring topology; and an error manager to determine, based on the received packet, whether an error occurred in transmission of the packet within the system, and the command engine being configured to selectively reissue the packet if the error manager determines that the error occurred at a specific position in the ring topology.