发明名称 |
Semiconductor device |
摘要 |
A semiconductor device according to the present invention includes a first address generation unit that includes a first register group and generates a table address by a cyclically repeating first pattern using a value stored to the first register group, a second address generation unit that includes a second register group and generates an access address by a cyclically repeating second pattern using a value stored to the second register group and parameter information determined by the table address, and a control unit that outputs setting information to be supplied to the first register group and the second register group. Further, the semiconductor device performs at least one of a read process and a write process of data from and to a data memory using the access address. |
申请公布号 |
US8880846(B2) |
申请公布日期 |
2014.11.04 |
申请号 |
US201313739562 |
申请日期 |
2013.01.11 |
申请人 |
Renesas Electronics Corporation |
发明人 |
Nakajima Hiroyuki;Ueno Shigeyuki |
分类号 |
G06F12/10;H04L1/00;H03M13/29;H03M13/00;G06F12/02;H03M13/41;G06F9/34 |
主分类号 |
G06F12/10 |
代理机构 |
Sughrue Mion, PLLC |
代理人 |
Sughrue Mion, PLLC |
主权项 |
1. A semiconductor device comprising:
a first address generation unit that includes a first register group and generates a table address by a cyclically repeating first pattern using a value stored to the first register group; a second address generation unit that includes a second register group and generates an access address by a cyclically repeating second pattern using a value stored to the second register group and parameter information determined by the table address; and a control unit that outputs setting information to be supplied to the first register group and the second register group, wherein the semiconductor device performs at least one of a read process and a write process of data from and to a data memory using the access address. |
地址 |
Kanagawa JP |