| 发明名称 | Method and apparatus for controlling state information retention in an apparatus | ||
| 摘要 | A method and apparatus for controlling state information retention determines at least a state information save or restore condition for at least one processing circuit such as one or more CPU or GPU cores or pipelines, in an integrated circuit. In response to determining the state information save or restore condition, the method and apparatus controls either or both of saving or restoring of state information for different virtual machines operating on the processing circuit, into corresponding on-die persistent passive variable resistance memory. The state information save or restore condition is a virtual machine level state information save or restore condition. State information for each of differing virtual machines is saved or restored from differing on-die passive variable resistance memory cells that are assigned on a per-virtual machine basis. | ||
| 申请公布号 | US8879301(B2) | 申请公布日期 | 2014.11.04 |
| 申请号 | US201213616142 | 申请日期 | 2012.09.14 |
| 申请人 | Advanced Micro Devices, Inc. | 发明人 | Mayhew David;Hummel Mark;Ignatowski Michael |
| 分类号 | G11C11/00;G11C13/00;G11C14/00;H03K19/00;G11C11/412;G11C5/00 | 主分类号 | G11C11/00 |
| 代理机构 | Faegre Baker Daniels LLP | 代理人 | Faegre Baker Daniels LLP |
| 主权项 | 1. A method for controlling state information retention in an apparatus comprising: determining at least a state information save or restore condition for at least one processing circuit in an integrated circuit die; and in response to determining the condition, controlling at least one of saving or restoring of state information for different virtual machines operating on the processing circuit into or from corresponding on-die passive variable resistance memory. | ||
| 地址 | Sunnyvale CA US | ||