Methods of forming field effect transistors on substrates

摘要

The invention includes methods of forming field effect transistors. In one implementation, the invention encompasses a method of forming a field effect transistor on a substrate, where the field effect transistor comprises a pair of conductively doped source/drain regions, a channel region received intermediate the pair of source/drain regions, and a transistor gate received operably proximate the channel region. Such implementation includes conducting a dopant activation anneal of the pair of source/drain regions prior to depositing material from which a conductive portion of the transistor gate is made. Other aspects and implementations are contemplated.

主权项

1. A method of forming a field effect transistor on a substrate, the field effect transistor comprising a pair of source/drain regions, a channel region received intermediate and elevationally below the pair of source/drain regions, and a transistor gate received operably proximate the channel region, the method comprising:
providing a pair of trench isolation regions extending into a background doped semiconductive material over a substrate; ion implanting conductivity enhancing impurity dopant into the background doped semiconductive material between the pair of trench isolation regions to form highest dopant concentration portions of the pair of source/drain regions, the highest dopant concentration portions comprising 1×1013 to 1×1016 ions/cm3; conducting a dopant activation anneal, the semiconductive material having an exposed uppermost surface during the implanting and the anneal; prior to conducting the dopant activation anneal, ion implanting conductivity modifying impurity dopant into semiconductive material of the substrate to form at least one lower dopant concentration portion proximate each highest dopant concentration portion, the conductivity modifying impurity dopant being of an opposite conductivity type than dopant in the highest conductivity concentration portions; after the dopant activation anneal, etching an opening through the highest dopant concentration portion and lower dopant portion and into the background doped semiconductive material, the opening extending to a first depth that is less than a second depth to which the isolation regions extend; and depositing material from which a conductive portion of the transistor gate is made into the opening.