发明名称 Memory control and data processing using memory address generation based on differential addresses
摘要 A memory control device that transfers data from an external memory to a data processing unit having plural processing mechanisms, includes an absolute address storage unit that stores an absolute address serving as a common reference value in a given data transfer period; a differential address storage unit that stores plural differential addresses therein; a differential address selection unit that selects any one of the plurality of differential addresses in a given order; a memory address generation unit that combines any differential address selected by the differential address selection unit with the absolute address to generate a memory address; and a data transfer unit that inputs the memory address generated by the memory address generation unit to the external memory, reads the data from the memory address, and transfers the data to the data processing unit.
申请公布号 US8880848(B2) 申请公布日期 2014.11.04
申请号 US201213619448 申请日期 2012.09.14
申请人 Renesas Electronics Corporation 发明人 Ninomiya Yasuyuki
分类号 G06F12/02;G06F13/28 主分类号 G06F12/02
代理机构 McDermott Will & Emery LLP 代理人 McDermott Will & Emery LLP
主权项 1. A memory control device that transfers data from an external memory to a data processing unit having a plurality of processing mechanisms, the memory control device comprising: an absolute address storage unit that stores an absolute address serving as a common reference value in a given data transfer period; a differential address storage unit that stores a plurality of differential addresses therein, each of the differential addresses indicating a difference between a read address and the absolute address; a differential address selection unit that selects any one of the plurality of differential addresses in a given order; a memory address generation unit that combines any differential address selected by the differential address selection unit with the absolute address to generate a memory address; and a data transfer unit that inputs the memory address generated by the memory address generation unit to the external memory, reads the data from the memory address, and transfers the data to the data processing unit.
地址 Kanagawa JP