Analysis of stress impact on transistor performance

摘要

Roughly described, a method for approximating stress-induced mobility enhancement in a channel region in an integrated circuit layout, including approximating the stress at each of a plurality of sample points in the channel, converting the stress approximation at each of the sample points to a respective mobility enhancement value, and averaging the mobility enhancement values at all the sample points. The method enables integrated circuit stress analysis that takes into account stresses contributed by multiple stress generation mechanisms, stresses having vector components other than along the length of the channel, and stress contributions (including mitigations) due to the presence of other structures in the neighborhood of the channel region under study, other than the nearest STI interfaces. The method also enables stress analysis of large layout regions and even full-chip layouts, without incurring the computation costs of a full TCAD simulation.

主权项

1. A system for developing an integrated circuit device in which mobility in a channel of a transistor of the circuit will be modified by stress effects, wherein:
the system is configured to determine an approximation of the stress in each of a plurality of sites in the channel, including for at least a subject one of the sites determining an approximation of the stress in a first dimension and an approximation of the stress in a second dimension different from the first dimension; the system is configured to convert each of the stress approximations to a respective mobility variation value; and the system is configured to provide for simulating the circuit, a combined mobility variation value for the transistor obtained in dependence upon a combination of the mobility variation values developed in the act of converting.