Magnetic memory circuit with stress inducing layer

摘要

Memory circuit comprising an addressable magnetic tunnel junction (MTJ) stack, forming a magnetic storage element in the circuit. The MTJ stack comprises a tunnel oxide layer between a free layer and a fixed layer. A stress inducing layer is disposed adjacent to the free layer to provide tensile or compressive stress to the free layer, in order to manipulate a magnetic field that is required to write a bit into the MTJ stack. Method of using the memory circuit is also proposed.

主权项

1. A memory circuit comprising:
a plurality of magnetic tunnel junction (MTJ) stacks forming a corresponding plurality of magnetic storage elements in the memory circuit, wherein each of the plurality of MTJ stacks includes:
a tunnel oxide layer between a free layer and a fixed layer; anda stress-inducing layer disposed above the free layer, wherein:
a first free layer of a first MTJ stack of the plurality of MTJ stacks is stressed to a first extent by a first stress-inducing layer of the first MTJ stack;a second free layer of a second MTJ stack of the plurality of MTJ stacks is stressed to a second extent by a second stress inducing layer of the second MTJ stack; andthe first extent and the second extent are different.