发明名称 |
Semiconductor integrated circuit device and supply voltage supervisor |
摘要 |
A semiconductor integrated circuit device includes a power-supply terminal to which a power-supply voltage is input; and multiple MOS transistors including an Nch deplete mode MOS transistor functioning as a current source and at least one Pch enhancement mode MOS transistor formed on a silicon-on-insulator substrate including a silicon substrate, a buried-oxide film, and a silicon activate layer, each of the multiple MOS transistors dimensioned so that a bottom of a source diffusion layer and a bottom of a drain diffusion layer reach the buried-oxide film, the at least one Pch enhancement mode MOS transistor being connected to the supply terminal through the Nch depletion mode MOS transistor. The Nch depletion mode MOS transistor has electrical characteristics such that a source voltage thereof is higher than a silicon substrate voltage thereof and a saturation current of the Nch depletion mode MOS transistor is decreased. |
申请公布号 |
US8878599(B2) |
申请公布日期 |
2014.11.04 |
申请号 |
US201113196983 |
申请日期 |
2011.08.03 |
申请人 |
Ricoh Company, Ltd. |
发明人 |
Negoro Takaaki |
分类号 |
G06F1/00;G06F3/16;G06F1/28;H01L27/088;H01L27/092;G06F1/30;H01L27/12 |
主分类号 |
G06F1/00 |
代理机构 |
Cooper & Dunham LLP |
代理人 |
Cooper & Dunham LLP |
主权项 |
1. A semiconductor integrated circuit device comprising:
a power-supply terminal to which a power-supply voltage is input; and multiple MOS transistors including an Nch deplete mode MOS transistor functioning as a current source and at least one Pch enhancement mode MOS transistor formed on a silicon-on-insulator substrate including a silicon substrate, a buried-oxide film, and a silicon activate layer, each of the multiple MOS transistors dimensioned so that a bottom of a source diffusion layer and a bottom of a drain diffusion layer reach the buried-oxide film, the at least one Pch enhancement mode MOS transistor being connected to the supply terminal through the Nch depletion mode MOS transistor, wherein the Nch depletion mode MOS transistor has electrical characteristics such that a source voltage thereof is higher than a silicon substrate voltage thereof and a saturation current of the Nch depletion mode MOS transistor is decreased. |
地址 |
Tokyo JP |