Conditional ALU instruction pre-shift-generated carry flag propagation between microinstructions in read-port limited register file microprocessor

摘要

A microprocessor includes a hardware instruction translator that translates an architectural instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the shift operation on the first source operand to generate the first result and a carry flag value and updates a non-architectural carry flag with the generated carry flag value. To execute the second microinstruction, it performs the second operation on the first result and the second operand to generate the second result and new condition flag values based on the second result. If a architectural condition flags satisfy the condition, it updates the architectural carry flag with the non-architectural carry flag value and updates at least one of the other architectural condition flags with the corresponding generated new condition flag values; otherwise, it updates the architectural condition flags with the current value of the architectural condition flags.

主权项

1. A microprocessor having architectural condition flags that include an architectural carry flag and other architectural condition flags, wherein the microprocessor performs an architectural instruction that instructs the microprocessor to perform a shift operation on a first source operand to generate a first result, to perform a second operation on the first result and a second operand to generate a second result, and to write the second result to a destination register and update the condition flags only if the architectural condition flags satisfy a condition specified in the architectural instruction, the microprocessor comprising:
a register, that includes storage for the architectural condition flags and includes storage for a non-architectural carry flag; a hardware instruction translator, that receives the architectural instruction and responsively translates the architectural instruction into first and second microinstructions; and an execution pipeline, that executes the microinstructions received from the hardware instruction translator; wherein in response to the first microinstruction, the execution pipeline:
performs the shift operation on the first source operand to generate the first result and a carry flag value; andupdates the non-architectural carry flag with the generated carry flag value; wherein in response to the second microinstruction, the execution pipeline:
performs the second operation on the first result and the second operand to generate the second result and new condition flag values based on the second result; andif the architectural condition flags satisfy the condition, updates the architectural carry flag with the non-architectural carry flag value and updates at least one of the other architectural condition flags with the corresponding generated new condition flag values; andif the architectural condition flags do not satisfy the condition, updates the architectural condition flags with the current value of the architectural condition flags.