发明名称 APPARATUS AND METHOD FOR FAST PHASE LOCKED LOOP(PLL) SETTLING FOR CELLULAR TIME-DIVISION DUPLEX(TDD) COMMUNICATIONS SYSTEMS
摘要 <p>A communications device is disclosed that adjusts a target signal to allow a reference phase locked loop (PLL) to lock onto a reference signal that is related to a desired operating frequency in a first mode of operation. The reference PLL locks onto the reference signal when the target signal is calibrated to be proportional to the reference signal. As the communications device transitions between the first mode of operation and a second mode of operation, the communications device performs a shorten calibration cycle on the reference PLL. The reference phase locked loop (PLL) locks onto the reference signal in response to the shorten calibration cycle in the second mode of operation.</p>
申请公布号 KR101436979(B1) 申请公布日期 2014.11.03
申请号 KR20120124360 申请日期 2012.11.05
申请人 发明人
分类号 H03L7/06;H04L25/02 主分类号 H03L7/06
代理机构 代理人
主权项
地址