| 摘要 |
<p>The present invention relates to an output signal correction device of an FPGA (field programmable gate array) based memory test device and a method thereof comprising; a clock generator (1) which outputs clock signals of different phases; and a pattern generator (2) which outputs an address signal, a data signal, and a clock signal by receiving the clock signal from the clock generator (1) and outputs a signal by correcting each timing of a plurality of output signals through flip-flop for timing measurement. According to the present invention as above, a correction time can be reduced without the composition of an external delay device by forming an output regarding the address signal, the data signal, and the clock signal outputted from the pattern generator as a programmable logic such as the FPGA. The present invention improves the performance (accuracy) of a memory tester by increasing the accuracy of timing of a signal outputted according to a memory test.</p> |
