HIERARCHICAL RECONFIGURABLE COMPUTER ARCHITECTURE

摘要

A reconfigurable hierarchical computer architecture having N levels, where N is an integer value greater than one, wherein said N levels include a first level including a first computation block including a first data input, a first data output and a plurality of computing nodes interconnected by a first connecting mechanism, each computing node including an input port, a functional unit and an output port, the first connecting mechanism capable of connecting each output port to the input port of each other computing node; and a second level including a second computation block including a second data input, a second data output and a plurality of the first computation blocks interconnected by a second connecting means for selectively connecting the first data output of each of the first computation blocks and the second data input to each of the first data inputs and for selectively connecting each of the first data outputs to the second data output.

主权项

1. A reconfigurable hierarchical computer architecture comprising:
in a first level of the hierarchical computer architecture, two or more computing nodes interconnected by a first level interconnection device to form a cluster; in a second level of the hierarchical computer architecture, two or more clusters interconnected by a second level interconnecting device to form a computing sub-block; and a microsequence memory programmed to dynamically control the first level interconnection device and/or the second level interconnection device during program execution.