PIPELINE ANALOG-TO-DIGITAL CONVERTER

摘要

A pipeline analog-to-digital converter is disclosed which includes at least one periodic unit consisting of two adjacent stages that jointly use two capacitor networks of the same structure. Each of the capacitor networks includes two identical capacitors, two switches and four terminals. On/off states of the switches and interconnection configuration of the terminals are controlled by clock signals to switch the periodic unit between four possible connection configurations. During operation of the periodic unit, when the upstream stage is in a sampling phase that involves one of the capacitor networks as well as a reference capacitor, the downstream stage uses the other of the capacitor networks to conduct residue amplification; and on the other hand, when the upstream stage is using one of the capacitor networks for residue amplification, the downstream stage relies also on this capacitor network for sampling, leaving the other of the capacitor networks idle.

主权项

1. A pipeline analog-to-digital converter (ADC), comprising:
a plurality of stages, wherein a first stage of the plurality of stages is adapted to receive an external analog signal and each of the plurality of stages is adapted to output an analog signal serving as an input analog signal for a next stage, wherein each odd-number-th stage and an adjacent next even-number-th stage thereof form a periodic unit; a first capacitor network and a second capacitor network for each periodic unit, the first and second capacitor networks both coupled to a corresponding periodic unit and having an identical structure; a first clock signal and a second clock signal inverted in phase and both coupled to each periodic unit, wherein the first and second clock signals are adapted to control one of the odd-number-th and even-number-th stages of each periodic unit to operate in a sampling phase, and to control the other of the odd-number-th and even-number-th stages of each periodic unit to operate in a holding phase; and a third clock signal and a fourth clock signal inverted in phase and both coupled to each periodic unit, wherein the third and fourth clock signals are adapted to couple each first capacitor network to one of the odd-number-th and even-number-th stages of a corresponding periodic unit, and to couple each second capacitor network to the other of the odd-number-th and even-number-th stages of the corresponding periodic unit.