SCALABLE SPLIT GATE MEMORY CELL ARRAY

摘要

A split gate memory array includes a first row having memory cells; a second row having memory cells, wherein the second row is adjacent to the first row; and a plurality of segments. Each segment includes a first plurality of memory cells of the first row, a second plurality of memory cells of the second row, a first control gate portion which forms a control gate of each memory cell of the first plurality of memory cells, and a second control gate portion which forms a control gate of each memory cell of the second plurality of memory cells. The first control gate portion and the second control gate portion converge to a single control gate portion between neighboring segments of the plurality of segments.

主权项

1. A split gate memory array having a plurality of rows, comprising:
a first segment of split gate memory cells, comprising:
a first plurality of split gate memory cells along a first row of the first segment;a second plurality of split gate memory cells along a second row of the first segment, wherein the second row is adjacent the first row;a first control gate conductor which forms a control gate of each of the first plurality of split gate memory cells;a second control gate conductor which forms a control gate of each of the second plurality of split gate memory cells; anda row strap conductor which is physically connected between the first control gate conductor and the second control gate conductor; a second segment of split gate memory cells, comprising:
a first plurality of split gate memory cells along a first row of the second segment;a second plurality of split gate memory cells along a second row of the second segment, wherein the second row of the second segment is adjacent the first row of the second segment;a first control gate conductor which forms a control gate of each of the first plurality of split gate memory cells of the second segment;a second control gate conductor which forms a control gate of each of the second plurality of split gate memory cells of the second segment; anda row strap conductor which is physically connected between the first control gate conductor and the second control gate conductor; and a segment strap conductor physically connected between the row strap conductor of the first segment and the row strap conductor of the second segment.